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| Definition | ||
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Alias is a SystemVerilog coding technique to model bi-directional mapping for 'inout' ports or wires in a module. In particular, alias mapping is a direct connection of one inout port to another. Lets you give an alternative name for almost anything. Particularly useful for renaming a slice of an array, as it avoids the need to define a new signal or variable. Also allows one package to inherit procedures and functions from another package by aliasing them. |
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| Syntax | ||
alias AliasName [: Datatype] is Name [Signature];
Signature = [TypeName, ...] return TypeName
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| Placement | ||
| Will be described later. | ||
| Rules | ||
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Each signal used in alias statement needs to be same net type. A wire, inout etc. Each signal used in alias must be of same width. |
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| Things to remember | ||
| Synthesis | ||
| Example | ||
module tomap
(inout [2:0] A, B;);
// alias 1
alias B = {A[0], A[1], A[2]};
endmodule
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| See Also | ||